View LRS1329_333045.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY PRODUCT SPECIFICATIONS
(R)
Integrated Circuits Group
16M Flash and 2M SRAM
(Model No.: LRS1329)
Stacked Chip
LRS1329
Spec No.: MFM2-J11601 Issue Date: June 10, 1999
SHARP
l
LRS1329
Handle this document carefully for it contains material protected by international full or in part,. of this material is prohibited copyright law. Any reproduction, without the express written permission of the company. When using the products covered herein, please observe.the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). *Office electronics * Instrumentation and measuring *Machine tools -Audiovisual equipment *Home appliances * Communication equipment other equipment
l
than for trunk
lines
(2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating redundancy, and other appropriate measures into the design fail-sale operation, for ensuring reliability and safety of the equipment and the overall system. *Control and safety devices for airplanes, trains, transportation equipment * Mainframe computers -Traffic control systems . Gas leak detectors and automatic cutoff devices *Rescue and security equipment . Other safety devices and safety equipment,etc. automobiles, and other
(3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, . accuracy. * Aerospace equipment . Communications equipment for trunk lines *Control equipment for the nuclear power industry -Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding above three Paragraphs to a sales representative the interpretation of the company. herein to a sales of the
or
l
Please direct representative
all queries regarding of the company.
the products
covered
SHARP
LRS1329
1
Contents
1. Description
............................
2
4. Block Diagram
..........................
4
5. Command Definitions
for Flash
Memory
-*--*-*-----*----
5
8. Absolute
Maximum Ratings
...............f.....
8
9. Recommended DC Operating
Conditions
...............
8
10. pi*
Capacitance
. - . . . . . a . . . . . a . - . a s s s s s `- s - e
8
11. DC Electrical
Characteristics
- * - *- * * * +* - * - - * - * - *
9
12. AC Electrical
Characteristics
(Flash Memory)
-*-**-**-*-*-
11
13. AC Electrical
Characteristic's
(SRAM)
--*-*------*---*-
18
14. Data Retention 15. Notes
Characteristics
for SRM
*-*-*---*---*---
21 22
.................................
17. Design Consideration
............,............
24
SHARI=
LRS1329
2
Part 1 Overview 1. Description The LR S 1 3 2 9 is a combination memory organized as lMx16/2M flash memory and 256K x8 bit static RAM in one package. Features OPower ONot supply designed 72 pin or rated CSP as radiation hardened ) plastic package P-type bulk silicon. and SRAM has .... .... 2.7 v -25 to 3.6 V +85 `c ~8 bit
OOperat ing temperature
"c to
0
( LCSPO72-P-0811 P-type bulk silicon,
OFlash Flash
memory has
Memory Time current (Ihe current Read Word/Byte Block erase (The current Architecture Parameter Blocks/ Boot Location for F-V,, pin) for write F-V, .... 100 ns (Max.)
OAccess OOperating
pin) . . . - 25 mA (Max. t,U=200ns) . . . . 17 mA (Max.) . . . - 17 mA (Max.) * * * * 10 PA (Max. F-ZZF-Vcc-0. F-EsO. ZV, F-V&O. 2V, 2V)
ODeep power down current OOptimized Array Blocking
Two 4X-word/8K-byte Boot Blocks/ Six 4K-word/8K-byte Thirty-one 32X-word/64K-byte Main Blocks/ Top 0 Extended Cycling Capabi 1 i ty Erase Cycles Suspend to Read write ~100,000 Block Word/Byte write
0 Enhanced Automated Suspend Options
Block Erase Suspend to Nerd/Byte Block Erase Suspend to Read SRAM OAccess OOperat OStandby OData Time ing current current current .
.... .... .... .... ....
85 ns 30 d 3
&ax. > OhL > s)
mA (Max. t,, t,=lp
15 PA (Max.) 15 ,uA (Max.)
retention
SHARP
LRS1329
2. Pin Configuration
r INDEX
3
Block erase and Word/Byte Write : Vi, or V w, Read 1 V,, or V k,, Deep Power Down: VIL F7@ Write Protect (Flash) Two Boot Blocks Locked : ViL (With F-&V m,Erase/Write can operate to all block) F-BYTE Byte Enable (Flash); x8 mode: VIL, x16 mode: VI, Ready/Busy (Flash) F-RY/BY During an Erase or Write operation: V,, Block Erase and Word/Byte Write Suspend: High-Z Deep Power Down: V, DQ,to DQ, Data Input/Outputs (Common) F-DQ 8 to F-DQ is Data Inputs/Outputs (Flash) ; Not used in x8 mode. Power Supply (Flash) F-V,, Power Supply (SRAl4) s-"cc Write, Erase Power Supply (Flash) F-V,, Block Erase and Word/Byte Write : F-V,,=V,,, : Al 1 Blocks Locked 1 F-V,,SHARI=
3. Truth Table (*l) Flash Read output Disable Write Read output Disable Write Read Power Output Disable Write Standby Reset Down tes) *l. ' Power Standby *6 x L ' Standby *2,3,4 *6 *6 *6 *6 *6 *6 *6 H H XLXXLH H H SRAM Note *4.5 L H F-a F-B
LRS1329
4
F-3 L
F-E H
S-CE, S-GE, S-s
S*
*7 H L
x
F-DQ F-mtoDPh , to hu& H DOUT L DOUT 1 High-Z Bigh-Z x.7-. H L DIN DIN High-Z DOUT High-Z DIN DOUT High-Z
L H ' ' L H H L L H X H L x x x x x X
Standby
Reset Down
High-Z DIN
Bigh-2
*7
High-Z
L=V,,, H=V,, , X=H or L . Refer
to DC Characteristics.
*2. Command writes involving block erase or word/byte write are reliably executed when F-V,,+., and F-V,=2.7V to 3-W. Block erase or word/byte write with V,,.
.F-?i? i =-
> F-RY/?% 16M(x8/x16) b i t Flash memory F-D'& to F-W,,
F-X F-E F-m F* F-BYTE
:' + :> :T
+DQ, S-A,, S-E, s-c> S-OE S-IRE 4b I> j> ;> 2M (x8) bit SRAM
to W,
s-v,
S-GND
SHARP I 5 Command Definitions
LRS1329
for Flash Memory (*I)
5 I
Word/Byte Write Block Write Block Write Note) *l. Erase and Word/Byte Suspend Erase and Word/Byte Resume
2 1 1
*5 *5 *5
Wr i t,e Write Write
WA XA XA
4OH or 10H Boll DOH
Write
WA
WD
Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. ' *2. BUS operations are defined in 3. Truth Table. *3. XA=Any valid address within the device. IA=Identifier Code Address. BA=Address within the block being erased. WA=Address of memory location to be written. SRD=Data read from status register(See the next page"Status Register Definition"). WD=Data to be written at location WA. Data is latched on the rising edge of F-%?or F-5 (whichever goes high first). II&Data read from identifier codes. *4. See the Following Identifier Codes. *5. See the following Write Protection Alternatives.
Write Operation Block Erase or Word/Byte Write F-V,, VIL >V,, F-i@ X V "t v IH VIH F?@ X X X VIL VIH
Protection
Alternatives Effect
All Blocks Locked. All Blocks Locked. All Blocks Unlocked. 2 Boot Blocks Locked. All Blocks Unlocks.
SHARP
6. Status WSMS Register ESS 6 Definition ES 5
LRS1329
6
WBWS
4
VPPS
3 NOTES:
WBWSS
2
DPS
1
R
0
7
S R. 7= WRITE STATE MACHINE STATUS( W SMS) 1 = Ready 0 = Busy SR. 6= ERASE SUSPEND STATUS( ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed
Check RYm or SR.7 to determine block erase OI word/byte write completion. SR.6-0 are invalid whi 1e SR. 7="0".
SR.5=ERASESTATUS( ES ) 1 = Error in Block Erasure 0 = Successful Block Erase S R. 4= WORD/BYTE WRITE STATUS ( WBWS 1 = Error in Word/Byte Write 0 = Successful Word/Byte Write SR. 3= V,, STATUS ( VPPS ) 1 = F-V,, Low Detect, Operation 0 = F-V,, OK )
If both SR. 5 and SR.4 are "1"s after a block erase attempt, an improper command sequence was entered.
Abort
SR.3 does not provide a continuous of F-V,, level. The WSM interrogates
indication and
S R. 2 = WORD/BYTE WRITE SUSPENDED STATUS
(WBWSS)
1 =Word/ByteWrite 0 =Word/ByteWrite Suspended in Progress/Completed
indicates the F-V,, level only after Block Erase or Word/ByteWrite command sequences. SR.: is not guaranteed to reports accurate feedback on 1y when F-V, +Vepm,2.
S R . l= DEVICE PROTECT STATUS ( D P S ) 1 = F-`WP or F-@' Lock Detected, Operation Abort 0 = Unlock S R. 0 = RESERVEDFOR FUTURE ENBANCEMENTS 4,R >
The WSM interrogates the F-s and F-E only after Block Erase orWord/ByteWrite command sequences. It informs the system, depending on the attempted operation, if the F-w is not VIM, F-E is not Vm+ SR.0 is reserved for future use and should masked out when polling the status register. be
SHARP
Memory Map for Flash Memory
Address [A,.-hl
LRS1329
7
4K*word/8K-byte 4K-word/BK-byte 4K-word/BK-byte 32K-word/64K-byte 32X-word/64K-byte 323.word/64K-byte 32K-word/64K-byte 32K-word/64K.byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-aord/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32X-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte 32K-word/64K-byte
Parameter Parameter Parameter Main Main Main Main Main Main Main Main Main Main Main Main tdain Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main Main
Block
Block
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block I
I ~~~
32K-word/64K-byte
19 MSB
18 X8
17
.....
2
1
0 LSB
20 YSB
19
18 X16
.....
2
1
0 LSB
Mode
Mode
I
SHARP
8.Absolute Maximum Ratings Parameter * Supply voltage (*l, 2) Input voltage (*l, 3) Operating Storage F-E Notes) *l. temperature temperature
LRS1329
I?
Symbo 1 Vcc VIN TOPT T, F-;pr F-E voltage -0.2 -0.5 -0.2 -25 -65
Ratings -0.2 (*4) to to to (*4) to 04 to +4.6 +85 +125 +14.0(*5) +14.0(*5) respect to to vcc+o.3
Unit V V `c c V V .
F-V,, voltage (*l) voltage (*l) The maximum applicable
on any pins with
CND.
*2. Except F-V,,. *3. Except F-E. *4. -2.OV undershoot *5. i-14.OV overshoot is allowed is allowed when the pulse width when the pulse width is less is less than 20nsec. than 20nsec.
9.Recommended DC Operating Parameter Supply voltage Input voltage
Conditions (T,= -25 "c to +85 Max. 3.6 v,+o. (*2) 0.8 12.6 3(*1) "c Unit V v V V than 20nsec. ) Min. 2.7 2.2 -0.2 11.4 TYP. 3.0
Symbo1 v, VIII VIL v, (*3)
Notes)
*1. V, is the lower one of S-V,, and F-V, _ *2. -2.OV undershoot is allowed when the pulse width *3. This voltage is applicable to F-B Pin only.
is less
10. Pin Capacitance Parameter Input Note) capacitance I/O capac i tance Symbo 1 Crw CI/o Condition
vIN=ov
(T,=25r, Min. TYP.
f=lMHz) kx. 20 22 Unit pF pF *I *l
VI/o=oV
*1 Sampled but not 100% Jested
SHARI=
11. DC Characteristics
LRS1329
9
Character Parameter Input leakage current )utput' F-V, leakage current V, Standby Current (Iti) (IJ Symbo 1 ILX
Ll
istics
(T.= -25 "r: to +85 Conditions
c,
V,=
2.7V
to 3.6V)
G#pJy
V,, =V, or CND
bcs
(*2,7)
=V, or GND VOIR F-E=F-3=F-V, fO.2V F--%F-V, fO.2V or F-CNDfO. 2V F-z=F -@=V,, F-%`=V,, or VIL
-1.5 25
+1.5 50
pA PA
0.2
2mA
Deep Power-Down
V, Read Current
Current
:-%=F-CNDfO. 2V,
bCD (*7)
LOUT (F-RY~bC-mA
MOS Input :-Cj?=F-GND, f=5Mlz. I,,, =OmA I TL Input %=F-GND, f=SMBz, Iom =omA F-V, =vpp, F-Vpp=vpp" I cm I,,, I PPS
I PPP I PPD
II
I
I
I
I
I4mA
I
J,, Word/Byte Write Current V, Block Erase Current J, Word/Byte Write Block !rase Suspend Current VP, St andby or ReadCurrent V, Deep Power-Down
F-CE=V,, F-V,, = F-V,, F-V, > F-V,, F-@=F-GNDfO. 2V F-V, =v,,,
F - `4, =VPPII
I I I6b
I I I
T-VPI
Current fpp Word/Byte Write Curren I PW
VP, Block Erase `Current
I,,
Word/Byte Write or
S-V,
slack Erase Suspend Zurrent Standby Current
I PPE I PPIS I PPES I SB
ISBl
F-V, =V,,,
.
,I I lo1 pA 2ool
I I I I
S-CE,, s-cE.&s-v,-0.2v or S-CE,IO. 2V
15 3.0
pA
DlA
S-CE,=V,aor S- CEa=ViL s -CE,=V,,, s -C&=V,,
VIN=VI~ or V,II
Operation Current
I cc1
t ,,=Min. II/O=omA t cYa.B=~s P Im--om 3o DlA
I cc2
s -CE,=o.2v, s-C&=S-vcc-0.2v VIN=S-vCC-O. 2V or 0.2V
I I I 31*
I I I I
SHARP
DC Characteristics (Continue)
LRS1329
-25'c to +ss"c , V,= 2.7 V to 3.6v)
10
Notes) 1. Reference values at V,=3.OV and T,=+25"C. 2. Includes F-RY/BY. 3. Automatic Power Savings (APS) for Flash Memory reduces typical I,,, to 3mA at 2.7V V, in static operation. 4. CMOS inputs are either V, fO.2V or GNMO.2V. TTL inputs are either Vi, or Vi,. 5. Block erases and word/byte writes are inhibited when F-V,, SV,,, and not guaranteed in the range between V,, (max) and V,, (min), and above V,, (max). 6. F-3 connection to a V, supply is allowed for a maximum cumulative 7. F-m is V&O.2V in word mode and is CWO.2V in byte mode. F-@ is V&O.ZV or CNDztO. 2V. period of 80 hours.
SHARP
12. Flash memory AC Characteristics AC Test Condtions Input pulse level Input Input ~ Output rise load and fall time Ref. level and Output timing
LRS1329
11
0 v to 2.7 ns 5 1.35 V lTTLfc, (30pF)
V
Read Cycle
CT,= -25C
to
+SS"c
) v,(y 2.7
to
3.6V )
Notes) Write
*l.
F-n Cycle
may be delayed (F-E Controlled)
up to tuQ,-k,,after (*2) Parameter
the falling (T,= -25C
edge of F-OEwithout to +85"c
impact to
on t,, 3.6V)
, V$ 2.7v Min. Max.
Unit
Write F-E F-w
Recovery
before
Read SRD, F-RY/BTHigh SRD, F-RY/B?High Z Z SRD, F-RY/k@-High
hHCL WL
F-V,, Hold from Valid
0 0 0 0
ns ns ns ns ns
1 I
V,,,,Hold from Valid Vi, Hold from Valid
t9VPH t9VSL hlH
I
1
F-BYTE Setup to F-E Going High F-BYTE Hold from F% Hinh
50
I
tn
100
ns
I
SHARP
Write Cycle (F-z Control led) (*2)
LRS1329
(T,= -25C to +85X ) V,F 2.7v to 3.6v)
12
Notes)
*2. Read timing characteristics during block erase and word/byte write operations are th same as during read-only operations. Refer to AC Characteristics for Read Cycle. *3. Refer to Section 5. Flash Memory Command Definition for valid &N and DIN for block erase or word/byte write.
LRS1329
Block Erase and Word/Byte Write Performance
(T,= -25C
to
+85 c,
V,= 2.7 V to 3.6 V j
hHav2 t MPVZ
Block Erase Time
32K-word 64K-byte 4K-word 8K-byte
Block Block Block Block
1.2 0.5 7.5 19.3 8.6 23.6
s s
huur
hnRz1
Word/ByteWrite Latency
Suspend Time ^- --. __ - _--
PS P's
Time to Read
hm3z2 hlmz2
Erase Suspend Latency to Read
SHARP
Flash Memory AC Characteristic Read Cycle timing chart
LRS1329
Timing Chart Device Address Selection Address Stable L Data Valid
Address
DQ
HIGH Z
F-V,
F-BYTE timing
Waveform Standby
Device Address Selection Address Stable
Data Valid
Address m
F-BYTE
)ATA (D/Q> (IQ,-W>
HIGH Z
c
DATA @/Cl) HIGH Z
t AVPV
k
I
t Pm
HIGH Z
SHARP
Write cycle timeng chart *1 I-l-A Address *2 (F-E
LRS1329
controlled) , *6 ,_
F-E
w
F-Bm
F-RY/BY
t,
L
(
b.L
F-WP
/ \
himlII>
hWH) l-
F-i@
(
~Wvll
>
tjt
am
F-V,,
Notes: *l. V,, Power -up and standby. *2. Write block erase or word/byte write setup. *3. Write block erase confirm or valid address and data. *4. Automated erase or program delay. *5. Read status register data. *6. Write Read Array command.
SHARP
Write cycle timing *1 l-V--%
Address
LRS1329
chart (F-E controlled) A
16
F-E
F-Z
F-E
w
F-BYTE
F-RY/BY
Notes: *l. V,, Power-up and standby. *2. Write block erase or word/byte write setup. *3. Write block erase confirm or valid address and data. *4. Automated erase or program delay. *5. Read status register data. %. Wri te Read Array command.
SHARP
Reset Operations Parameter
LRS1329
(T,= -25 `c to +85 `c , SW. is not true hz h 100 Min. 100 23.6 Vcc= 2.7V to 3.6 V ) Max. Unit ns ,u s ns *1,2 *3
17
F-E Pulse Low Time (If F-E.is tied to Vcc, this specification applicable.) F?@ Low to Reset during Block Erase or Write F-V,, 2.7V to F-B High iotes)*l.
If F-B is asserted while a block erase or word/bytewrite operation is not executing, the reset will complete with loons. *2. A reset time, t,,. is required from the later of F-RY/BY going High Z of F-E going high until outputs are valid. *3. When the device power-up, holding F-3 low minimum 1oOns is required after Vcc has been in predefined range and also has been in stable there.
AC Waveform for Reset Oneration
High Z FRY/BY @) voL VIII F -@ (P) VI, \ (
t,m
/ ) (A)Reset During Read Array Mode
High Z F-RY/BY(R) VOL
I( tpu.2
7
>
VIII F-B (P) VIL
r ( t,LPil I>
.
(B)Reset During Block Erase or Word/Byte
Write
F-i@(P) (C)F-E Rising Timing
SHARP
13. SRAM AC Electrical SRAM AC Test Conditions Input pulse Input 1Output Note) rise load *l. Including scope and jig Input and level and fall Output time timing Ref.level Characteristics
LRS1329
18
I
0.4 v to 2.2 5 ns 1.5 llTLtC, (30pF) V (*l)
v
capacitance.
Read
Cycle (T,= -25 Parameter =C to +85 `c Min. 85 85 85 85 , v,= 2.7Vto3.6 Max. Unit ns ns ns ns V) .
Sym. hc hA
Read Cycle Time Address access time time(S-E) Chip enable access
hcE1
(s-c&J
hca
*2 *2 *2 *2 *2 *2
Write
Cycle (T,= -25 "c to +85 C , v,=2.7 V to 3.6 V )
S-z L S-B
High to output Low to output output for
active in High impedance
t 01 t,
5 0 25 active into tests
ns ns
*2 *2
*2. Active specified
to High impedance and High impedance to output a f20OmV transition from steady state levels
the test
load.
SHARP
SRAM AC Charaterestics Read cycle timing Timing Chart chart(*3)
LRS1329
19
Address
s -CE,
S-C&
S-X
DOOI
*3 S%? is high for Read cycle. Write cycle timing chart(S-E Controlled)
Address
< Jf
tic
> `(
S-OE
S-CE,
S-CE,
t OIL?
(*I <
'
I tow > (*lo)
DOUT
\\\\\\\\\\\\\\
trn
,, /'
km
DIN
(*8)
/ \
Data Valid
SHARI=
Write cycle timing chart-(S-aLow
LRS1329
20
fixed)
Address
Dwr // / , , , , , II I I (*s) DIN I, < / ta ./ /`A Data Valid
tm
I-
Notes) *4. A write A write A write and S-E *5. *6. *7. a. *9. *10. occurs begins during the overlap low. transition of S-going valid among S-z, going high, of write S-CE, going low twis measured from the beginning to the end of write. of a low SE,, among S-m a high S-C& and a low S-x, going low, S-CE,going
at the latest
transition
high and S-mgoing going high.
ends at the earliest from the later
tcr is measured tAs is measured tm is measured During signals If S-E, If S-XI S-E this
low or S-C& going high of write. therefore the input
to the end of write.
. from the address W pins
to the beginning to the address state,
from the end of write
change.
period,
are in the output
of opposite
phase to the outputs
must not be applied. with with S-E S% going low or after
goes low or S-C& low, the outputs
goes high simultaneously remain in high remain in high goes low simultaneously
S-WE going
impedance state. going high or impedance state.
goes high or S-C& the outputs
going high,
SHARP
14.SRAM Data Retention Characteristics
LRS1329
21
(T,= Parameter Data Retention Supply volotage Data Retention Supply current Chip enable setup time
bDR
-25C
to
+35"c Max. 3.6 Unit V
>
sym.
Conditions
Min. 2.0
Typ. (*l)
VCCDB S-C& SO. 2V or S-CE,~V,w-O. 2v (*2> I cccm v,,=3v S-C&SO. S-E 2V or (*2) LV,,-0.2v
0.2
15
pA ns
0 5
Chip enable hold time Notes) tR
lCS
*l. Reference value at T,=25'c, S-V,=3. OV. *2. S-CE,ZV,-O.2V, S-CE.&V,-0.2V (S-E, control
led) or S-C&SO.
2V (S-C&
control
led)
Data Retention
timing
chart
(S-%Controlled)(*3)
L
Data Retention
mode
.
()v --.---I
-_---
-.-----s-e-
____I__.___..._ _...-.....- -_ -I-..._- -I_ .
... ....--.. --
Data Retention
timing
chart
(S-CEz Control led) / Data Retention
. .._. _. .. ..__._._-_..__._._ ._-_.--.-__-. CDP
mode
-VCC . CE,
2.JV
- . ....---..
_.. . ...- -i-`
/ _.-._.... _.._. .. ... .. .. .. . _..__.._ _..__ .. .. ...-_.... _..._.._...__.._----_
.
. . .. .. .. .. .. ...
,
0. 8
v
___.._..__.___ ________._. __________________.........~ _.__.____.____.______ _ __.____. ___________.__._______...................... ._..___._.__.........................
_. . .. .. .. ._.. .. ..
Note) *3. To control the data retention mode at S-z,, fix the input level of S-C& between V,, and Vcc, -0.2V or OV or 0.2V and during the data retetion
mode.
SHARP
LRS1329
22
15. Notes This product is a stacked CSp package that a 2M (x8) bit SWAMare assembled into. and a Supply Power Maximum difference
16M(x8/x16)
bit
Flash Memory
(between F-V,x and S-V,)
of the voltage
is less than 0.3V.
Power Supply and Chip Enable of Flash Memory and SRAM S-E1 should not be LOW and S-Q should not be BIGH when F-Eis LOW simulataneously. .If the two memories are active together, possibly they may not operate normally by interference noises or data collision on W bus. Both F-V, and S-V, are needed to be applied by the recommended supply voltage at the same time except SWAMdata retention mode. Power UP Sequence When turping on Flash memory power supply, keep F-B LOW. After F-V,, reaches over 2.7V, keep F-a LOW for more than 100nsec. Device Decoupling The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between SWAMand Flash Memory. Note peak current caused by transition of control signals (F-E, S-CE,, S-C&).
SHARP
16.Flash Memory Data Protection
LRS1329
23
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-W signal or power supply may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block By setting a F?? to low, only the boot block can be protected Parameter and main blocks cannot be locked. System program, etc., can be locked by storing them in the boot When a high voltage is applied to F-E, overwrite operation is For further information on setting/resetting of block bit,and refer to the specification. (See 5.Command Definitions P.5)
against
overwriting.
block. enabled for all blocks. controlling of F-e and F-D,
2) Data protection through Vpp When the level of Vpp is lower than VPPLK(lockout voltage), write operation on the flash memory is disabled. All blacks are locked and the data in the blocks are completely write protected. For the lockout voltage, refer to the specification. (See Chapter 11. DC Characteristics P-10)
Data protection
during
voltage
transition operation on
1) Data protection thorough F-s When the F-E is kept low during power up and power down sequence, write the flash memory is disabled, write protecting all blocks. For the details of F-E control, refer to the specification. (See chapter AC Electrical.Characteristics)
.
12. Flash Memory
SHARF)
17. Design Considerations 1. Power Supply Decoupling
LRS1329
24
To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a O.lpF ceramic capacitor connected between its V, and GND and between its V,,and CND. Low inductance capacitors should be placed as close as possible to package leads. 2. V,,Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the Vr, Power Supply trace. Use similar trace widths and layout considerations given to the Vcc power bus. 3. The Inhibition of Overwrite Operation
Please do not execute reprogramming "0" for'the bit which has already been programed "0". Overwrite operation may generate unerasable bit. In case of reprogramming "0" to the data which has been programed "1". * Program "0" for the bit in which you want to change data from "1" to "0". * Program "1" for the bit which has already been programmed "0". For example, changing data from "1011110110111101" "1110111111111110" programming. 4. Power Supply Block erase, full chip erase, word/byte write and lock-bit configuration with an invalid V,,(See 11. DC Characteristics) produce spurious results and should not be attempted. Device operations at invalid Vcc voltage(see ll.DC Characteristics) produce spurious results and should not be attempted. to "1010110110111100" requires
I
INDEX
I
I
TOP
VIEW-,--
---e-e
-i-
-----a
01 6 -- +o
0
0
I :
0 ai
---
----.
0
1
\\\ ,1' \i\ i /` II I' \/ ----____ 1 I 1 u c-1 ,:\j, I\ \\ ,II "
0. 8 TYP. 0. 4 TYP.
1. 1 TYP. =
/
,=
I
I
to
C
a 4
BOTTOM
I ?z000bOL!000OOO " 0000~0000
P oooo;ooo~
0000~0000
\
OJ 3 \/ /I
I
ti c a, d v
I 1 1
I
--VIEW
m .----e-vP
"
0 0 0 oT~~~j-cc.---OOOOiOOOO 0000~0000
4 5 6,171 6 9101112
m
I
I
~0000601000000 123
i=?ESSCALE
WI UNIT
l=l/lmm
slF%H
APPL t
16M
FLASH
+ZM
.yEMORYCXL6aa) SRAM CXSI
c.4aLz
5/l
SC'b'J71
MODEL
MATRIX
LCSPO72-P-081
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Fax: (360) 834-8903 http://www.sharpsma.com
SHARP Microelectronics Europe Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Fax: (49) 40 2376-2232 http://www.sharpsme.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Fax: +81-743-65-1532 http://www.sharp.co.jp

▲Up To Search▲

Price & Availability of LRS1329

	To Download LRS1329 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .